Machine Control Instructions in 8085 Microprocessor includes the instructions related to interrupts and the instruction used to stop the program execution.
Machine Control Instructions in 8085
Explanation of Instruction
No operation is performed. The instruction is fetched and decoded. However no operation is executed.
Halt and enter wait state
The CPU finishes executing the current instruction and halts any further execution. An interrupt or reset is necessary to exit from the halt state.
The interrupt enable flip-flop is reset and all the interrupts except the TRAP are disabled. No flags are affected.
The interrupt enable flip-flop is set and all interrupts are enabled. No flags are affected. After a system reset or the acknowledgement of an interrupt, the interrupt enable flip-flop is reset, thus disabling the interrupts. This instruction is
Apart from above instructions two more machine control instructions are explained below.
RIM and SIM Instruction in 8085 Microprocessor
This is a multipurpose instruction used to read the status of interrupts 7.5, 6.5, 5.5 and read serial data input bit. The instruction loads eight bits in the accumulator with the following interpretations.
- The RIM (Read Interrupt Mask) instruction is a single-byte instruction in the 8085 microprocessor that is used to read the contents of the interrupt mask register (IMR).
- The IMR is an 8-bit register that is used to enable or disable interrupts in the 8085 microprocessor.
When the RIM instruction is executed, the 8085 microprocessor reads the contents of the IMR and stores the result in the accumulator register (A).
The IMR can be used to enable or disable any of the five interrupts in the 8085 microprocessor, including:
- INTR: This is the maskable interrupt that is triggered by an external signal on the INTR pin.
- RST 7.5: This is a maskable interrupt that can be triggered by the RST 7.5 pin.
- RST 6.5: This is a maskable interrupt that can be triggered by the RST 6.5 pin.
- RST 5.5: This is a maskable interrupt that can be triggered by the RST 5.5 pin.
- SID: This is a non-maskable interrupt that is triggered by a signal on the SID pin.
- The IMR is divided into two halves, with the upper four bits controlling the RST 7.5, RST 6.5, and RST 5.5 interrupts, and the lower four bits controlling the INTR and SID interrupts.
- Each bit in the IMR can be set to either 1 or 0, with a value of 1 enabling the corresponding interrupt and a value of 0 disabling it.
- When the RIM instruction is executed, the current status of the IMR is read and stored in the accumulator.
- The contents of the IMR can then be used by the program to determine which interrupts are enabled and which are disabled.
This is a multipurpose instruction and used to implement the 8085 interrupts 7.5, 6.5, 5.5, and serial data output. The instruction interprets the accumulator contents as follows.
SOD — Serial Output Data: Bit D7 of the accumulator is latched into the SOD output line and made available to a serial peripheral if bit D6 = 1.
SDE — Serial Data Enable: If this bit = 1, it enables the serial output. To implement serial output, this bit needs to be enabled.
XXX —Don’t Care
R7.5—Reset RST 7.5: If this bit = 1, RST 7.5 flip-flop is reset. This is an additional control to reset RST 7.5.
MSE— Mask Set Enable: If this bit is high, it enables the functions of bits D2, D1, D0.
This is a master control over all the interrupt masking bits. If this bit is low. bits D2, D1, and D0, do not have any effect on the masks.
M7.5—D2 = 0, RST 7.5 is enabled.
= 1, RST 7.5 is masked or disabled.
M6.5—D1, = 0, RST6.5 is enabled.
= 1, RST 6.5 is masked or disabled.
M5.5—D0 = 0, RST 5.5 is enabled.
= 1, RST 5.5 is masked or disabled.
- Syntax: SIM
- The SIM instruction sets the interrupt mask to the value in the accumulator. The interrupt mask determines which interrupts are enabled and which are disabled.
- When an interrupt occurs, the microprocessor checks the interrupt mask to see if that interrupt is enabled.
- If the interrupt is enabled, the microprocessor executes the corresponding interrupt service routine (ISR). If the interrupt is disabled, the microprocessor ignores it.
Operation: The SIM instruction performs the following operations:
- The contents of the accumulator are loaded into the interrupt mask register.
- The interrupt enable flip-flops (IE0, IE1) are set to their previous state. This means that if an interrupt was previously enabled, it remains enabled, and if it was previously disabled, it remains disabled.
Flags: The SIM instruction does not affect any flags in the flags register.
Example: Suppose we want to enable the RST 5.5 interrupt and disable all other interrupts. We can do this using the following code:
MVI A, 20H ; Load the interrupt mask into the accumulator
SIM ; Set the interrupt mask
HLT ; Halt the microprocessor
In this example, the value 20H in the accumulator sets the interrupt mask to 00100000 in binary, which enables the RST 5.5 interrupt and disables all other interrupts.
- Note that the SIM instruction is used in conjunction with the RIM (Read Interrupt Mask) instruction, which reads the current interrupt mask from the interrupt mask register into the accumulator.
- Together, these instructions provide a mechanism for enabling and disabling interrupts in the 8085 microprocessor.