The 8255 is a widely used, programmable, parallel I/O device. It can be programmed to transfer data under various conditions, from simple I/O to interrupt I/O. It is flexible, versatile and economical and complex.
Lets see how to interface 8255 with 8085 microprocessor.
Features of 8255
- Three 8-bit IO ports PA, PB, PC
- PA can be set for Modes 0, 1, 2. PB for 0,1 and PC for mode 0 and for BSR. Modes 1 and 2 are interrupt driven.
- PC has two 4-bit parts: PC upper (PCU) and PC lower (PCL), each can be set independently for I or O. Each PC bit can be set/reset individually in BSR mode.
- PA and PCU are Group A (GA) and PB and PCL are Group B (GB)
- Address/data bus must be externally demultiplexed.
- TTL compatible.
- Improved dc driving capability.
Block Diagram of 8255
Data Bus Buffer: This three-state bi-directional 8-bit buffer is used to interface the 8255 to the system data bus.
Data is transmitted or received by the buffer upon execution of input or output instructions by the CPU. Control words and status information are also transferred through the data bus buffer.
Read/Write and Control Logic: The function of this block is to manage all of the internal and external transfers of both Data and Control or Status words. It accepts inputs from the CPU Address and Control busses and in turn, issues commands to both of the Control Groups.
Chip Select (CS): A “low” on this input pin enables the communication between the 8255 and the CPU.
Read (RD): A “low” on this input pin enables 8255 to send the data or status information to the CPU on the data bus. In essence, it allows the CPU to “read from” the 8255.
Write (WR): A “low” on this input pin enables the CPU to write data or control words into the 8255.
(A0 and A1) Port Select 0 and Port Select 1: These input signals, in conjunction with the RD and WR inputs, control the selection of one of the three ports or the control word register. They are normally connected to the least significant bits of the address bus (A0 and A1).
(RESET) Reset. A “high” on this input initializes the control register to 9Bh and all ports (A, B, C) are set to the input mode.
Group A and Group B Controls of 8255
- The functional configuration of each port is programmed by the systems software. In essence, the CPU “outputs” a control word to the 8255.
- The control word contains information such as “mode”, “bit set”, “bit reset”, etc., that initializes the functional configuration of the 8255.
- Each of the Control blocks (Group A and Group B) accepts “commands” from the Read/Write Control logic, receives “control words” from the internal data bus and issues the proper commands to its associated ports.
Group A and Group B Controls
- The functional configuration of each port is programmed by the systems software. In essence, the CPU “outputs” a control word to the 8255.
- The control word contains information such as “mode”, “bit set”, “bit reset”, etc., that initializes the functional configuration of the 8255.
- Each of the Control blocks (Group A and Group B) accepts “commands” from the Read/Write Control logic, receives “control words” from the internal data bus and issues the proper commands to its associated ports.
Ports A, B, and C
The 8255 contains three 8-bit ports (A, B, and C). All can be configured to a wide variety of functional characteristics by the system software but each has its own special features to further enhance the power and flexibility of the 8255.
· Port A One 8-bit data output latch/buffer and one 8-bit data input latch. Both “pull-up” and “pull-down” bus-hold devices are present on Port A.
· Port B One 8-bit data input/output latch/buffer and one 8-bit data input buffer.
· Port C One 8-bit data output latch/buffer and one 8-bit data input buffer (no latch for input). This port can be divided into two 4-bit ports under the mode control.
· Each 4-bit port contains a 4-bit latch and it can be used for the control signal output and status signal inputs in conjunction with ports A and B.
Operational modes of 8255
There are two basic operational modes of 8255:
- Bit set/reset Mode (BSR Mode).
- Input/output Mode (I/O Mode).
The two modes are selected on the basis of the value present at the D7 bit of the Control Word Register. When D7 = 1, 8255 operates in I/O mode and when D7 = 0, it operates in the BSR mode.
Bit set/reset (BSR) mode
The Bit Set/Reset (BSR) mode is applicable to port C only. Each line of port C (PC0 – PC7) can be set/reset by suitably loading the control word register. BSR mode and I/O mode are independent and selection of BSR mode does not affect the operation of other ports in I/O mode.
- D7 bit is always 0 for BSR mode.
- Bits D6, D5 and D4 are don’t care bits.
- Bits D3, D2 and D1 are used to select the pin of Port C.
- Bit D0 is used to set/reset the selected pin of Port C.
Input/Output mode
This mode is selected when D7 bit of the Control Word Register is 1. There are three I/O modes:
- Mode 0 – Simple I/O
- Mode 1 – Strobed I/O
- Mode 2 – Strobed Bi-directional I/O
D0, D1, D3, D4 are assigned for lower port C, port B, upper port C and port A respectively. When these bits are 1, the corresponding port acts as an input port.
For example, if D0 = D4 = 1, then lower port C and port A act as input ports. If these bits are 0, then the corresponding port acts as an output port.
If D1 = D3 = 0, then port B and upper port C act as output ports. D2 is used for mode selection of Group B (port B and lower port C). When D2 = 0, mode 0 is selected and when D2 = 1, mode 1 is selected.
Mode 0 – Simple I/O
In this mode, the ports can be used for simple I/O operations without handshaking signals. Port A, port B provide simple I/O operation. The two halves of port C can be either used together as an additional 8-bit port, or they can be used as individual 4-bit ports. Since the two halves of port C are independent, they may be used such that one-half is initialized as an input port while the other half is initialized as an output port.
- The input/output features in mode 0 are as follows:
- Output ports are latched.
- Input ports are buffered, not latched.
- Ports do not have handshake or interrupt capability.
- With 4 ports, 16 different combinations of I/O are possible.
Mode 0 – input mode
- In the input mode, the 8255 gets data from the external peripheral ports and the CPU reads the received data via its data bus.
- The CPU first selects the 8255 chip by making CS’ low. It then selects the desired port using A0 and A1 lines.
- The CPU then issues an RD’ signal to read the data from the external peripheral device via the system data bus.
Mode 0 – Output mode
- In the output mode, the CPU sends data to 8255 via system data bus and then the external peripheral ports receive this data via 8255 port.
- CPU first selects the 8255 chip by making CS’ low. It then selects the desired port using A0 and A1 lines.
- CPU then issues a WR’ signal to write data to the selected port via the system data bus. This data is then received by the external peripheral device connected to the selected port.
Mode 1
When we wish to use port A or port B for handshake (strobed) input or output operation, we initialise that port in mode 1 (port A and port B can be initialised to operate in different modes, i.e., for e.g., port A can operate in mode 0 and port B in mode 1).
Some of the pins of port C function as handshake lines. For port B in this mode (irrespective of whether is acting as an input port or output port), PC0, PC1 and PC2 pins function as handshake lines.
If port A is initialised as mode 1 input port, then, PC3, PC4 and PC5 function as handshake signals. Pins PC6 and PC7 are available for use as input/output lines.
The mode 1 which supports handshaking has following features:
- Two ports i.e. port A and B can be used as 8-bit i/o ports.
- Each port uses three lines of port c as handshake signal and remaining two signals can be used as i/o ports.
- Interrupt logic is supported.
- Input and Output data are latched.
Input Handshaking signals
- IBF (Input Buffer Full)-It is an output indicating that the input latch contains information.
- STB (Strobed Input)-The strobe input loads data into the port latch, which holds the information until it is input to the microprocessor via the IN instruction.
- INTR (Interrupt request)-It is an output that requests an interrupt. The INTR pin becomes a logic 1 when the STB input returns to a logic 1, and is cleared when the data are input from the port by the microprocessor.
- INTE (Interrupt enable)-It is neither an input nor an output; it is an internal bit programmed via the port PC4(port A) or PC2(port B) bit position.
Output Handshaking signals
- OBF (Output Buffer Full)-It is an output that goes low whenever data are output (OUT) to the port A or port B latch. This signal is set to a logic 1 whenever the ACK pulse returns from the external device.
- ACK (Acknowledge)-It causes the OBF pin to return to a logic 1 level. The ACK signal is a response from an external device, indicating that it has received the data from the 82C55 port.
- INTR (Interrupt request)-It is a signal that often interrupts the microprocessor when the external device receives the data via the signal. this pin is qualified by the internal INTE (interrupt enable) bit.
- INTE (Interrupt enable)-It is neither an input nor an output; it is an internal bit programmed to enable or disable the INTR pin. The INTE A bit is programmed using the PC6 bit and INTE B is programmed using the PC2 bit.
Mode 2
- Only group A can be initialised in this mode. Port A can be used for bidirectional handshake data transfer. This means that data can be input or output on the same eight lines (PA0 – PA7).
- Pins PC4 – PC7 are used as handshake lines for port A. The remaining pins of port C (PC0 – PC3) can be used as input/output lines if group B is initialised in mode 0 or as handshaking for port b if group B is initialised in mode 1.
- In this mode, the 8255 may be used to extend the system bus to a slave microprocessor or to transfer data bytes to and from a floppy disk controller.
