In VHDL, the architecture body of an entity can be expressed in various ways. In this article, data flow style of modelling in VHDL is explained with example.
As specified in previous article, the internal details of an entity are specified by an architecture body using any of the following modelling styles:
- As a set of interconnected components (Structural style of modelling),
- As a set of concurrent assignment statements (Data flow style of modelling),
- As a set of sequential assignment statements (Behavioral style of modelling),
- Any combination of the above three (Hybrid style of modelling).
Data Flow Style of Modelling in VHDL
In this modelling style, the flow of data through the entity is expressed primarily using concurrent signal assignment statements. The structure of the entity is not clearly specified in this modelling style, but it can be indirectly deduced.
Example 1: Half Adder Using Data Flow Style of Modelling
Entity for Half adder
entity HALF_ADDER is
port (A,B: in bit;
Sum, Carry: out bit);
Architecture for Half adder
Such a model for the HALF_ADDER entity is described in an architecture body that uses data flow as shown below.
architecture Data_HA of HALF_ADDER is
Sum <= A xor B;
Carry <= A and B;
The name of the architecture body is Data_HA. The dataflow model for the HALF_ADDER is described using two concurrent signal assignment statements.
In a signal assignment statement, the symbol <= indicates an assignment of a value to a signal. The value of the expression on the right-hand-side of the statement is computed and is assigned to the signal on the left-hand side, called the target signal.
A concurrent signal assignment statement is executed only when any signal used in the expression on the right-hand side the value for the signal changes.
Concurrent signal assignment statements are parallel statements, and therefore, the ordering of these statements in an architecture body is not important. Hence, two statements can also be written as
Carry <= A and B;
Sum <= A xor B;
Example 2: 2 to 4 Decoder Using Data Flow Style of Modelling
Entity for 2:4 decoder
entity DECODER24 is
port (A, B: in bit;
D: out BIT_VECTOR(0 to 3));
Architecture for 2:4 decoder
Here is a dataflow model for the DECODER24 entity.
architecture Dec_dataflow of DECODER24 is
signal ABAR, BBAR: BIT;
ABAR <= not A; — Statement 1
BBAR <= not B; — Statement 2
D(0) <= (ABAR and BBAR); — Statement 3
D(1) <= (ABAR and B); — Statement 4
D(2) <= (A and BBAR); — Statement 5
D(3 ) <= (A and B) after 5 ns; — Statement 6
The architecture body consists of one signal declaration and six concurrent signal assignment statements. The signal declaration declares signals ABAR and BBAR to be used locally within the architecture body.
Delay information is included in the last signal assignment statement (statement 6) using after clause. In other signal assignment statements, no after clause was used to specify delay. In all such cases, a default delay of 0 ns is assumed.
This delay of 0 ns is also known as delta delay, and it represents an infinitesimally small delay. This small delay corresponds to a zero delay with respect to simulation time and does not correspond to any real simulation time.
To understand the behavior of above architecture body, consider a change in input signal signals, say at input port A at time T. This would cause the concurrent signal assignment statements 1,5, and 6, to be triggered. Their right-hand side expressions would be evaluated and the corresponding values would be programmed to be assigned to the target signals at time (T+Δ).
When simulation time advances to (T+ Δ), new values to signals ABAR, D(2) and D(3), are assigned. Since the value of ABAR changes, this will in turn trigger signal assignment statements, 3 and 4. Eventually, at time (T+2Δ), signals D(0) and D(1) will be assigned their new values.
Also note that, concurrent signal assignment statements are parallel statements, and therefore, the sequence of above statements in an architecture body is not important. Hence, the statements after keyword begin may be written in any order.