Behavioral Style of Modelling

In VHDL, the architecture body of an entity can be expressed in many ways. In this article, Behavioral Style of Modelling in VHDL is explained with example.

As specified in previous articles, the internal details of an entity are specified by an architecture body using any of the following modelling styles:

  1. As a set of interconnected components (Structural style of modelling),
  2. As a set of concurrent assignment statements (Data flow style of modelling),
  3. As a set of sequential assignment statements (Behavioral style of modelling),
  4. Any combination of the above three (Hybrid style of modelling).

Behavioral Style of Modelling in VHDL

In contrast to the styles of modelling described earlier, the Behavioral style of modelling specifies the behavior of an entity as a set of statements that are executed sequentially in the specified order.

This set of sequential statements, that are specified inside a process statement, do not explicitly specify the structure of the entity but merely specifies its functionality.

Process Statement

A process statement is a concurrent statement that can appear within an architecture body.

A process statement has

  1. A declarative part (between the keywords process and begin).
  2. A statement part (between the keywords begin and end process).

The statements appearing within the statement part are sequential statements and are executed sequentially.


[process_label:] process [(sensitivity list)] [is]

[process item declarations];


{sequential statement/s};

end process [process label];

Note: Everything in [ ] is optional.

The list of signals specified within the parenthesis after the keyword process constitutes a sensitivity list and the process statement is invoked whenever there is an event on any signal in this list.

Process places only one driver on the signal. The value that the signal is updated with, is the last value assigned to it within the process execution.

Example: Y<= A and B;

Y<= C or D;

It won’t create two drivers. Y will get the value generated by last statement ‘C or D’.

It is not allowed to declare signals or shared variables inside the processes. The process should either have ‘sensitivity list’ or ‘wait statement’ at the end.

A process never terminates. It is always either being executed or in a suspended state. The wait statement is used to suspend process. (Discussed later.)

For example, consider the following behavioral model for the DECODER24 entity.

Example 1: 2 to 4 Decoder Using Behavioral Style of Modelling

structural modelling of 2 to 4 decoder, Structural Style of Modelling, behavioral style of modelling,

Entity for 2:4 decoder


port(A, B:in bit;

D: outBIT_VECTOR(0to3));


Architecture for 2:4 decoder

Here is a Behavioral model for the entity DECODER24.

architecture Dec_Behavioral of DECODER24 is


process (A, B)

variable ABAR, BBAR: BIT;


 ABAR := not A; — statement 1

 BBAR := not B; — statement 2

 D(3) <= A and B; — statement 3

 D(0) <= ABAR and BBAR; — statement 4

 D(2) <= A and BBAR; — statement 5

 D(1 ) <= ABAR and B; — statement 6

end process;

end Dec_Behavioral;

  • In this example, when an event occurs on signals A or B the statements appearing within the process statement are executed sequentially.
  • The variable declaration (starts with the keyword variable) declares two variables called ABAR and BBAR. A variable is different from a signal.

The difference between Variable and Signal is explained in the following article. You can read it by clicking on the link below.

Data Objects in VHDL with Examples (
  • Signal assignment statements appearing within a process are called sequential signal assignment statements.
  • Sequential signal assignment statements, including variable assignment statements, are executed sequentially independent of whether an event occurs on any signals in its right-hand side expression or not.
  • Contrast this with the execution of concurrent signal assignment statements in the dataflow modelling style.
  • In this architecture body, if an event occurs on any signal. A or B, statement 1 which is a variable assignment statement, is executed, then statement 2 is executed, then statement 3 and so on.
  • It is possible to use case or loop statements within a process. It will be discussed in subsequent blogs in details.

Example 2: D Flip-flop using Behavioral Style of Modelling

Behavioral Style of Modelling

Entity for D flip-flop

entity DFF is

port (D, CLK: in BIT;

Q, QBAR: out BIT);

end DFF;

Architecture for D flip-flop

architecture DFF_Behavioral of DFF is


 process (D, CLK)


if (CLK = ‘1’) then

Q <= D;

QBAR<= not D;

end if;

 end process;

end DFF_Behavioral;

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