In this article, entity and architecture declaration in VHDL are discussed with examples. Let us first learn about some lexical elements used in VHDL.
Lexical Elements
The lexical elements are the basic units in a VHDL program.
- comments,
- identifiers,
- reserved words,
- number, characters and strings.
Comments
- The comments are for documentation purpose only. It does not have any effect on VHDL program.
- Comments are specified in the language by preceding the text with two consecutive dashes (–). All text between the two dashes and the end of that line is treated as a comment.
– – Text in this line is considered as comment upto the end of line.
– – This is a valid comment
Y<= A and B; — This is also a valid comment
Identifier
- Identifiersare user-defined words used to names for signals, variables, constants, as well as entities, architectures and so on in VHDL models.
- An identifier in VHDL is composed of a sequence of one or more characters. A legal character is an upper-case letter (A… Z), or a lower-case letter (a. .. z), or a digit (0 . . . 9) or the underscore ( _ ) character.
- The first character in an identifier must be a letter and last character mustNOTbe “_”.
- VHDL language isNOTcase sensitive. Lower-case and upper-case letters are considered to be identical when used in an identifier. For example. Name, NAME, and NamE, all refer to the same identifier.
- Two successive underscores “_ _” areNOT
Examples of valid identifiers are: MUX41, Dec_38, efy_vhdl1.
Some invalid identifiers are: _MUC81, my_ckt@input, gate-input, double_ _score.
Keywords in VHDL
The following words are VHDL keywords (also called reserved words) and cannot be used for identifiers (signal names, process names, entity names, etc…).
VHDL Reserved Words (Keywords) are
abs | access | after | alias |
all | and | architecture | array |
assert | attribute | begin | block |
body | buffer | bus | case |
component | configuration | constant | disconnect |
downto | else | elsif | end |
entity | exit | file | for |
function | generate | generic | group |
guarded | if | impure | in |
inertial | inout | is | label |
library | linkage | literal | loop |
map | mod | nand | new |
next | nor | not | null |
of | on | open | or |
others | out | package | port |
postponed | procedure | process | pure |
range | record | register | reject |
rem | report | return | rol |
ror | select | severity | signal |
shared | sla | sll | sra |
srl | subtype | then | to |
transport | type | unaffected | units |
until | use | variable | wait |
when | while | with | xnor |
xor |
Numbers, Characters and Strings
A Number in VHDL can be
integer, such as 0, 1212, and 2E16
real, such as 0., 1.23456, or 9.87E6
represented in other number bases:
45 = 2#101101# – – 2 indicates Binary number and ‘101101’ is value of 45 in binary
38 = 16#26# – – 16 indicates Hexadecimal number and 26 is value of 38 in hexadecimal
A character in VHDL is enclosed in single quotation marks,
such as ‘E’, ‘Z’, ‘0’, ‘1’.
1 and ‘1’ are different.
A string in VHDL is a sequence of characters enclosed in double quotation marks,
such as “EFY”, “101101”.
2#101101# and “101101” are different
Entity Declaration
- An entity is the most building block in VHDL. It gives the external views of the design. Enitity declaration defines the external view of the design that is description of the input and output ports of the design.
- Each port in the description must be given a name, data flow direction and type. Entity is the description of interface between design and external world.
- Entity does not know about internal behaviour of the component. It is equivalent to in configuration of IC.
- VHDL design description must include only one entity. One entity can be associated with many architectures. This means that declaration made in one entity can be visible in all architectures assigned to that entity.
Syntax:
entity entity_name is
port(port list);
end entity_name;
Let us write an entity for AND gate.
Same entity can also be declared as
entity AND_2 is
port ( A: in STD_LOGIC;
B : in STD_LOGIC;
Y : out STD_LOGIC);
end AND_2;
There are four different modes available in VHDL for ports
- in: input port
- out: output port
- inout: bidirectional port
- buffer: output port with read capability
Architecture declaration
- The architecture describes the underlying functionality or internal organization or operation of the entity and contains the statements that model the behaviour of the entity.
- A design can be described in an architecture using various level abstraction to facilitate faster design.
- Architecture body is used to describe the internal details of the design entity using following modelling styles.
- Behaviour: as a set of sequential assignment statements.
- Dataflow: As a set of concurrent statements
- Structure: As a set of interconnected components
- Mixed: As a set of combination of above three
Syntax:
architecture architecture_name of entity_name is
signal/component declaration;
begin
statements (relation between input and output);
end architecture_name;
- Single entity can have several architectures, but architecture cannot be assigned to different entities. Architecture may not be used without an entity.
- Architecture assigned to an entity describes internal relationship between input and output ports of the entity. It consists of two parts
- Declaration: It may contain declaration of types, signals, constants, subprograms, components and groups.
- Concurrent statements: Define the relationship between input and outputs.
Example:
