This VHDL tutorial provides VHDL basics. It is designed for beginners especially students. What is HDL? What is VHDL? What is History of VHDL? are explained in this tutorial. The key focus is on Need and features of VHDL.
- Digital circuit was changed from SSI to LSI in the year 1980s.
- Initially DeMorgan has attempted to reduce the digital design in small space by DeMorgan’s law, multiplexers, PLDs, SOP and POS methods were used. For this purpose, hardware was used.
- Now instead of doing it with hardware, software languages like Verilog systems and VLSI were emerged. These languages are known as HDL languages.
- Hardware description language (HDL) is the language that is used to describe the behaviour or structure of the system. Thus, in other words, HDL is a model of digital system with timing explicitly.
- VHDL is a hardware description language used for modelling digital system mode of an interconnection of components.
- VHDL is an acronym for VHSIC hardware description language and VHSIC is an acronym for very high-speed integrated circuit.
- VHDL is an industry standard language used to describe the hardware from abstract to specifying input and output from various design tools.
- Digital electronics designing using VHDL means the designer writes code in VHDL and then verifies the function using simulator after that the code is synthesized into a net list. Synthesis means a code is translated into schematic with gates and flip-flops.
History of VHDL
- The requirements for the language VHDL were first generated in 1981 under the VHSIC program
- In this program, a number of US companies were involved in designing VHSIC chip for the department of defense.
- At this time, most of the companies were using different Hardware Description Languages (HDL) to design and develop their IC.
- Different vendors give their chips different in different Hardware Description Languages (HDLs)
- Replacement and reuse become a big problem to department of defense. Thus, a need for a standardized Hardware Description Language (HDL) for the design, documentation and verification of digital system was generated.
- A team of companies like IBM, Texas instruments and Intermetrics were first awarded the contract by the department of defense to develop a version of the language in 1983,
- Version 7.2 of VHDL was developed and released to the public in 1985.
- After the release of version 7.2 used by companies, who were developing VHSIC chips found need to make the language an industry wide standard, Consequently, the language was upgraded with new features. The syntax of many constructs was made more uniform and many ambiguities present in the 1987 version were resolved and new version of VHDL is known as IEEE 1076-1995.
Need of VHDL
- Every electronics design engineer should learn and use a HDL language to keep pace with the productivity of competitors.
- Using VHDL, we can quickly describe and synthesize circuit of 20 thousand or more gates on a single chip.
- VDHL provides the capabilities. Therefore, there is a need of VHDL for digital design.
Features of VHDL
- Concurrent language: Concurrent statements execute at the same time in parallel as in hardware. VHDL basically works in a concurrent form. Here sequence of statement is not important
- Sequential language: Sequential statement may execute one at a time in sequence (if required) as in any conventional language. Sequence of statement is important. VHDL is the amalgamation of concurrent and sequential language.
- Netlist language: Net-list is produced after synthesizing VHDL code. Net-list is textual information of logic cells and their interconnections. It is in industry standard format named EDIF (Electronic Design Interchange Format). Net-list is used to exchange graphical and electronic data between EDA tools from various vendors.
- Timing specifications: Clocks of different frequencies can be generated by using VHDL. Time specifications can be assigned to the signals. VHDL supports both synchronous and asynchronous timing models.
- Test bench: Test benches can be written using VHDL to test other VHDL models. Test bench is a VHDL model that generates a set of test vectors and sends them to the module being tested. Tests are needed to ensure that the design is correct or not.
- Design hierarchy: Hierarchy can be represented using VHDL. Consider example of a full adder which is the top-level module, being composed by three lower level modules, i.e half adder and an OR gate. It means VHDL is a structural language.
- Supports deign libraries: The analyzed VHDL code can be inserted into a design library. The design library is a storage facility in which analyzed VHDL descriptions are stored. These design units can be used for any other design
- VHDL has powerful construct language, constructs such as if else, with select, case, when etc.
- VHDL has a nine value package standard logic 1164, so we can assign one of the value from nine values to the system.
- VHDL supports flexible design methodologies top-down, bottom-up or mixed.