The internal details of an entity are specified by an architecture body using any of the following modelling styles:
- As a set of interconnected components (to represent structure: Structural Style of Modelling),
- As a set of concurrent assignment statements (to represent dataflow: Data flow Style of Modelling),
- As a set of sequential assignment statements (to represent behavior: Behavioral Style of Modelling),
- Any combination of the above three (Hybrid Style of Modelling).
In this article, the structural style of modelling for the architecture is explained.
Structural Style of Modelling in VHDL
In the structural style of modelling, an entity is described as a set of interconnected components.
Example 1: Half adder using Structural style of modelling
Entity for Half adder
entity HALF_ADDER is
port (A,B: in bit;
Sum, Carry: out bit);
Architecture for Half adder
Such a model for the HALF_ADDER entity is described in an architecture body as shown below.
architecture Struct_HA of HALF_ADDER is
port (P, Q: in BIT; R: out BIT);
port (L, M: in BIT; N: out BIT);
X1: XOR2 port map (A, B, Sum);
A1: AND2 port map (A, B, Carry);
The name of the architecture body is Struct_HA. The entity declaration name is HALF_ADDER. The architecture body is composed of two parts:
- The declarative part (before the keyword begin) and
- The statement part (after the keyword begin).
As shown in the diagram, the half adder consists of one AND gate and one Ex-OR gate. Hence, two component declarations AND and XOR are present in the declarative part of the architecture body.
These declarations specify the interface of components that are used in the architecture body. The components XOR2 and AND2 may either be predefined components in a library, or if they do not exist, they may later be bound to other components in a library.
The declared components are instantiated in the statement part of the architecture body using component instantiation statements. XI and A1 are the component labels for these component instantiations.
The first component instantiation statement, labelled XI, shows that signals A and B (the input ports of the HALF_ADDER), are connected to the P and Q input ports of a XOR2 component, while output port R of this component is connected to output port Sum of the HALF_ADDER entity.
Similarly, in the second component instantiation statement, signals A and B are connected to ports L and M of the AND2 component, while port N is connected to the CARRY port of the HALF_ADDER.
Note that in this case, the signals in the port map of a component instantiation and the port signals in the component declaration are related by position (called positional association). The structural representation for the HALF_ADDER does not say anything about its functionality.
Separate entity models would be described for the components XOR2 and AND2, each having its own entity declaration and architecture body.
Example 2: 2 to 4 Decoder using Structural Style of Modelling
Entity for 2:4 decoder
entity DECODER24 is
port (A, B: in bit;
D: out BIT_VECTOR(0 to 3));
Architecture for 2:4 decoder
architecture Struct_Dec of DECODER24 is
port (A: in BIT; Z: out BIT);
port (A, B: in BIT; Z: out BIT);
signal ABAR, BBAR: BIT;
I0: INV port map (A, ABAR);
I1: INV port map (B, BBAR);
A0: AND2 port map (ABAR, BBAR, D(0));
A1: AND2 port map (ABAR, B, D(1));
A2: AND2 port map (A, BBAR, D(2));
A3: AND2 port map (A, B, D(3));
In this example, the name of the architecture body is Struct_Dec, and it is associated with the entity declaration with the name DECODER24; therefore, it inherits the list of interface ports from that entity declaration.
In addition to the two component declarations (for INV and AND2), the architecture body contains a signal declaration that declares two signals, ABAR and BBAR, of type BIT. These signals, that represent wires, are used to connect the various components that form the decoder.
The scope of these signals is restricted to the architecture body, and therefore, these signals are not visible outside the architecture body. Contrast these signals with the ports of an entity declaration that are available for use within any architecture body associated with the entity declaration.
A component instantiation statement is a concurrent statement, as defined by the language. Therefore, the order of these statements is not important.
The structural style of modelling describes only an interconnection of components (viewed as black boxes) without implying any behavior of the components themselves, nor of the entity that they collectively represent.
In the architecture body Struct_Dec, the signals A and B, used in the component instantiation statements are the input ports declared in the DECODER24 entity declaration.
For example, in the component instantiation labelled A3, port A is connected to input A of component AND2, port B is connected to input port B of component AND2, and the output port Z of component AND2 is connected to port D(3) of the DECODER24 entity.
Again positional association is used to map signals in a port map of a component instantiation with the ports of a component specified in its declaration. The behavior of the components AND2 and INV are not apparent, nor is the behavior of the decoder entity that the structural model represents.