Data Types in VHDL

All the objects in VHDL can be declared using type specification. A wide range of data types in VHDL are available. A type declaration statement is

TYPE type_name is type_mark;

Two main data types in VHDL are

  1. Scalar Data Types
  2. Composite Data Types

Scalar Data Types in VHDL

The scalar data types describe objects that can hold at the most one value at a time. The type itself can contain multiple values.

  1. Integer types
  2. Real types
  3. Enumerated types
  4. Physical types

Integer types

They are like mathematical integers. An integer type defines a type whose set of values fall within a specified integer range.

For example:

type MUX16 is range 15 downto 0;

type length is range 0 to 10;

Integer is the only predefined integer type that covers the range from –(231 – 1) to +(231 -1).

Real types

They are used to declare objects that emulate mathematical real numbers. It has a set of values in the given range of real numbers.

For example:

type real data range 0.0 to 75.5;

The predefined real data type covers the range —1.0E38 to + 1.0E38, and it must provide at least six decimal digits of precision.

Enumerated types

This declaration defines a set of user defined values consisting of identifiers and character literals.

For example:

type micro_op is (load, store, add, sub, mul, div) ;

  • Hence micro_op is enumerated type and supports the values load, store, add, sub, etc.

             type MUL is (‘U’, ‘0’, ‘1’, Z’);

  • Similarly, MUL is an enumerated type that has the set of ordered values ‘U’, ’0’, ’1’ and ‘Z’. The order in which values appear in an enumeration type declaration defines their ordering i.e.,

                 store < div is true

                 sub > mul is false

The predetermined enumeration types are character, bit, Boolean and std_logic type.

  • The values belonging to the type character constitute 191 characters of the ISO eight-bit coded character set. These values are called character literals and are always two single quotes (‘’).

            For example: ‘A’, ‘_’, ‘5’

  • The predefined type bit has the literals ‘0’ and ‘1’.

For example:

type two_state is (‘0’ , ‘1’);

Variable clock: two_state;

Clock := 0;

  • While type Boolean has the literals false and true.

            For example: variable e_flag : boolean : = true ;

  • Type std_logic, defined in the package std logic_1164 of IEEE library is an enumerated type. It is defined as

type std_logic is (‘U’, ‘X’, ‘0’, ‘1’, ‘Z’, ‘W’, ‘L’, ‘H’, ‘-‘);

u = uninitialized

x = unknown

0= logic 0

1= logic 1

Z= high impedance

W= weak unknown

L= weak logic 0

H= weak logic 1

– = don’t care

Physical Types

They are used to represent real world quantities like length, voltage, time and current. Physical type includes the primary unit of measure another units that are integral multiple of this unit.

For example:

constant set_up : time: = 2 ns

type current is range 0 to 1E9


nA;                                          –nano amperes

uA=1000 nA;                           — micro amperes

mA=1000 uA;                          — milli amperes

Amp = 1000ma;                      — amperes

End units;

The base unit is nano ampere (nA), while all others derived units.

Composite Data Types in VHDL

Collection of values represented by composite type. It has two types namely:

  1. Array types
  2. Record types

Array types

An object of an array type consists of elements that have the same type.

For example:

signal D: std_logic_vetor (3 downto 0);

type ROM_bus is array (0 to 63) of data_word;

Record types

An object of a record type is composed of elements of same or different types.

For example:

type sc_type is range 0 to 10 3

type module is record

size – integer range 10 to 150 ;

critical_dly : time ;

No_ inputs – sc_type ;

No outputs – sc_type ;

end record;   

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