Data Objects in VHDL with Examples

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The objects are used to represent and store the data in the system being described in VHDL. It holds the values of specific type. The VHDL object consist of following objects.

  1. Constant
  2. Variable
  3. Signal

All these Data Objects in VHDL with Examples are explained in the following article.

Constant

  • These are the identifiers with fixed value. The value is assigned only once when declared. Constants object are the names assigned to specific values of a type.
  • Constants are the object in VHDL, whose value can not be changed once defined for the design. Model becomes more readable and easier to update by the use of constant.
  • A single value of a given type is assigned to the constant before simulation starts and the value can not be changed during the course of simulation.
  • Constants are assigned using the “:=” operator.

Syntax:

Constant constant_name : type_name := value;

Examples:

    1. constant pi : real := 3.14;
    2. constant voltage : integer := 5;
    3. constant propogation_delay time := 10ns;

Variable

  • Variables are the objects used to store a single current value and can be updated using VHDL sequential statements.
  • Variables must be declared inside a process statement and subprogram and they are local to those process throughout the entire simulation.
  • The different values can be assigned to the variable at different time using a variable assignment statement. The value assignments to the variable occur immediately.
  • In contrast to signal assignment, a variable assignment takes effect immediately. Variables are assigned using the “:=” operator.

Syntax:

Variable variable_name : type_name := initial value;

Examples:

    1. Variable A,B : bit;
    2. Variable Buses : std_logic_vector (7 downto 0);

How to use a variable inside the program, is explained as follows.

Process (var)

Variable a_var : integer := 5;

begin

a_var = a_var+2;

end process;

Initial value of variable a_var is 5. After assignment, new value of a_var will be 7.

Signal

  • Signals are the communication medium between the entities. It represents the wires within a circuit. Signals are used connect entities together to form models.
  • It holds a list of values which include the current value of the signal and the set of possible future values that are to appear on the signal.
  • Signals can be declared in entity declaration section, architecture declaration section and package declaration section.
  • Signal declared in entity declaration section are global to any architecture for that entity. Signals declared in architecture can only be referenced in that architecture only. Signals declared in package can be shared among entities and are called global signals.
  • The signal types in VHDL are: BIT, BIT_VECTOR, STD_LOGIC, STD_LOGIC_VECTOR, STD_ULOGIC, SIGNED, UNSIGNED, INTEGER, ENUMERATION and BOOLEAN.

Syntax:

Signal signal_name : signal_type := initial value;

Examples:

    1. Signal temp1: bit;
    2. Signal ground: std_logic :=0;
    3. Signal QBAR : bit_vector (2 downto 0);

How to use a signal inside the program, is explained as follows.

entity nor_gate is

port (A, B: in bit;

C: out bit);

end nor_gate;

architecture dataflow of nor_gate is

signal S: bit;

begin

S <= A or B;

C <= not S;

end architecture dataflow;

Difference Between Variable and Signal

Sr. No.

Category

Signal

Variable

1

Syntax

Signal signal_name : signal_type := initial value;

Can be used as:

Y <= ‘0’;

Y <= a and b;

Y <= “1010”;

Variable variable_name : type_name := initial value;

Can be used as:

Y := ‘0’;

Y := a + b;

Y := “1010”;

2

Place of Declaration

All places except process, function and procedures

Only inside process, functions and procedures

3

Scope

Throughout the code

Only inside the process, functions and procedures where declared

4

Assignment Operator

<=

:=

5

Memory required

More

Less

6

Updation

With a delay, updated once inside a process.

Immediate, can be updated number of times, the latest value can then be used.

7

Wait statement

It requires wait statement if value is to be updated for next statement usage

It does not require wait statement as the value is updated immediately

8

Converted to wire

Yes

No

For any query in Data Objects in VHDL with Examples please comment.

Recent posts

Related posts:

  1. VHDL Basics
  2. Pros and Cons of VHDL
  3. Operators in VHDL
  4. Data Types in VHDL
  5. Entity and Architecture Declaration in VHDL
  6. Structural Style of Modelling
  7. Data Flow Style of Modelling
  8. Behavioral Style of Modelling
  9. Sequential Statements in VHDL
  10. Concurrent Statements in VHDL
  11. Subprograms in VHDL
  12. Packages in VHDL
  13. VHDL Testbench

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