CPLD – Complex Programmable Logic Device

Complex Programmable Logic Device (CPLD) is one of the PLD. It is used for the implementation of the logical circuits. Lets see something about Programmable Logic Devices (PLDs) first.

Programmable Logic Devices (PLDs)

  • Variety of IC’s can have their logic function programmed into them after they are manufactured. Most of devices use technology that allows the functionto be reprogrammed which means that if you find a bug in your design you may be able to fix it without physically replacing or rewriting the device to be used.
  • These devices are called programmable logic devices. It consists of two-level structure of AND and OR gates with user programmable connections. A designer can accommodate any logic function up to a certain level of complexity in them.
  • PLDs have following advantages over other ICs
  1. Compact circuitry
  2. Low power requirement
  3. Higher switching speed
  4. Flexibility: New designs can be programmedeasily in few seconds
  5. Modifications in the design can be carriedout immediately just by reprogramming
  • PLDs are very popular because of these advantages. There are two types Of PLDs classified based onnumber of gates within the PLDs.
  • The basic AND-OR structure of PLDs could not be scaled to layer sizes. Hence for scaling larger designs Complex PLD (CPLD) is required. A typical CPLD is a collection of multiple PLDs and an interconnection structure, all on the same chip.
  • Compared to a CPLD, a Field Programmable Gate Array (FPGA) contains a much larger number of smaller individual logic blocks which is explained in next article.

Need of CPLD

  • The Programmable Logic Devices (PLDs) such as PLAs and PALs have limited number of inputs, product terms and outputs. These devices can support up to about 32 total number of inputs and outputs only.
  • For implementation of circuits that require more inputs and outputs than that are available in a single SPLD chip, either multiple SPLD chips can be employed. But this has also some limitations.
  • To overcome these limitations, more sophisticated chip like CPLD is needed to design the digital circuits.

Concept of CPLD

  • The complexity of any digital IC chip can be specified in terms of number of equivalent 2-input NAND gates.
  • A typical PAL has 8 macro cells, if each macro cell represents about 20 equivalent gates, than the PAL can accommodate a circuit that needs up to about 160 gates.
  • For a circuit requiring very large number of gates, CPLDs having large number of macrocells (say 512 macro cells) can implement circuits of up to about 10 thousand equivalent gates i.e. they are similar to SPLDs except that the CPLD is equivalent of 2 to 64 SPLDs.
Figure 1: General structure of a CPLD
  • A CPLD typically contains from tens to a few hundred macrocells.
  • They are as fast as PLAs but more
  • They are digital ICs that are just like a large number of PALs in a single silicon chip connected to each other through a cross point switch.

Architecture of CPLD

CPLD architecture block diagram
Figure 2: Architecture (Block diagram) of CPLD
  • It consists of a number of PAL like blocks, input/output blocks and a set of interconnection wires.
  • The PAL like blocks are connected to a set of interconnection wires and to an input/output block.
  • The input block is used to drive signals to the pins of the CPLD at the appropriate voltage levels with the appropriate current.
  • A PAL-like block (also called functional block) usually consists of 16 macro cells.
  • Each macro cell consists of an AND-OR configuration, an EX-OR gate a flip-flop, a multiplexer and a tristate buffer.
CPLD - Complex Programmable Logic Device
Figure 3: A typical macrocell of a CPLD
  • Each AND-OR configuration usually consists of 5 to 20 AND gates and an OR gate with 5 to 20 inputs.
  • An EX-OR gate is used to obtain the output of OR gate in an inverted or non-inverted form depending upon its other input being 1 or 0 respectively.
  • A tristate buffer acts as a switch, which enables the chips pin to be used output or as an input.
  • In case of chip pin is used as an input pin an external source can drive a signal on to the pin, which can be connected to other macro cells using the interconnection wiring.
  • When used as an input pin, the macro cell becomes redundant and it is wasted.

Advantages Of CPLDs

  • Ease of Design: With use of HDL and CPLD development tools.
  • Reduced Board Area.
  • Available in tiny sizes.
  • Due to less maintenance, lower Development Costs

Some of the families of CPLD

Some of the families of CPLD from different retailers include

  • Altera MAX 7000 and MAX 9000 families
  • Atmel ATF and ATV families
  • Lattice ISP LSI family
  • Lattice (Vantis) MACH family
  • Xilinx XC9500 family

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